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PM7346 参数 Datasheet PDF下载

PM7346图片预览
型号: PM7346
PDF下载: 下载PDF文件 查看货源
内容描述: SATURN QUAD用户网络接口, J2 , E3 , T3 [SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3]
分类和应用: 网络接口
文件页数/大小: 419 页 / 2502 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7346 S/UNI-QJET  
DATASHEET  
PMC-960835  
ISSUE 6  
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3  
codes are detected, and an integral HDLC receiver is provided to terminate  
the path maintenance data link.  
Provides frame synchronization for the G.751 or G.832 E3 applications, alarm  
detection, and accumulates line code violations, framing errors, parity errors,  
and FEBE events. In addition, in G.832, the Trail Trace is detected, and an  
integral HDLC receiver is provided to terminate either the Network  
Requirement or the General Purpose data link.  
Provides frame synchronization for G.704 and NTT 6.312 Mbit/s J2  
applications, alarm detection, and accumulates line code violations, framing  
errors, and CRC parity errors. An integral HDLC receiver is provided to  
terminate the data link.  
Provides frame synchronization, cell delineation and extraction for DS3,  
G.751 E3, G.832 E3, and G.704 and NTT J2 ATM direct-mapped formats.  
Provides PLCP frame synchronization, path overhead extraction, and cell  
extraction for DS1 PLCP, DS3 PLCP, E1 PLCP, and G.751 E3 PLCP  
formatted streams.  
Provides a 50 MHz 8-bit wide or 16-bit wide Utopia FIFO buffer in the receive  
path with parity support, and multi-PHY (Level 2) control signals.  
Provides ATM framing using cell delineation. ATM cell delineation may  
optionally be disabled to allow passing of all cell bytes regardless of cell  
delineation status.  
Provides cell descrambling, header check sequence (HCS) error detection,  
idle cell filtering, header descrambling (for use with PPP packets), and  
accumulates the number of received idle cells, the number of received cells  
written to the FIFO, and the number of HCS errors.  
Provides a four cell FIFO for rate decoupling between the line, and a higher  
layer processing entity. FIFO latency may be reduced by changing the  
number of operational cell FIFOs.  
Provides a receive HDLC controller with a 128-byte FIFO to accumulate data  
link information.  
Provides detection of yellow alarm and loss of frame (LOF), and accumulates  
BIP-8 errors, framing errors and FEBE events.  
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 3  
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