PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Registers 007H, 107H, 207H and 307H: Transmit Timing Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
FIFOBYP
XCLKSEL
Unused
OCLKSEL
TREF[1]
TREF[0]
Unused
0
0
0
0
0
0
X
X
R/W
R/W
R/W
Unused
When the T1 or E1 format is selected, these registers allow software to configure
the options of the transmit timing section.
FIFOBYP:
The FIFOBYP bit enables the transmit input signals to DJAT to be bypassed
around the FIFO to the outputs. When jitter attenuation is not being used,
the DJAT FIFO can be bypassed to reduce the delay through the transmitter
section by typically 24 bits. When FIFOBYP is set to logic 1, the inputs to
DJAT are routed around the FIFO to the outputs. When FIFOBYP is set to
logic 0, the transmit data passes through the DJAT FIFO. When the T1 or E1
format is not enabled, the FIFO is automatically bypassed.
XCLKSEL:
The XCLKSEL bit selects the source of the high-speed clock used in the
CDRC and FRMR blocks. When XCLKSEL is set to logic 1, the XCLK input
signal is used as the high-speed clock to these blocks. XCLK must be driven
with clock that is 8 times the nominal bit rate (12.352 MHz for T1 or 16.384
MHz for E1). When XCLKSEL is set to logic 0, the high-speed clock is driven
by XCLK divided by 3. XCLK must be driven with a clock that is 24 times the
nominal bit rate (37.056MHz for T1 or 49.152 MHz for E1). XCLK must be
set to logic 0 when jitter attenuation is enabled.
OCLKSEL:
The OCLKSEL bit selects the source of the Digital Jitter Attenuator FIFO
output clock signal. When OCLKSEL is set to logic 1, the DJAT FIFO output
clock is driven with the transmit reference clock as selected by the TREF[1:0]
inputs. In this mode the jitter attenuation is disabled and the input clock must
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
83
PMC [ PMC-SIERRA, INC ]
