PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
an analogous fashion. A clock pulse is generated on RDLCLK for each
enable that is logic 1. Any combination enable bits is allowed resulting in a
data rate between 4 kbit/s and 20 kbit/s.
If all RXSAEN[4:0] bits are set to logic 0, Timeslot 16 is extracted and treated
as a data link. If RXDMASIG is logic 0, Timeslot16 is made available on the
RDLSIG output and RDLCLK is an associated 64 kHz clock. If RXDMASIG is
logic 1, the data link is terminated by the HDLC receiver and the
RDLINT/RDLSIG and RDLEOM/RDLCLK pins operate as a data link interrupt
(RDLINT) and a end-of-message (RDLEOM) indication.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
81
PMC [ PMC-SIERRA, INC ]
