PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Figure 10
- E1 Jitter Tolerance
100
40
35
DJAT
10
minimum
tolerance
Jitter
Amplitude,
UI pp
1.5
1.0
acceptable
ITU G.823
unacceptable
Region
0.2
0.1
0.01
1
2.4k
18k
100
1k
10k
100k
10
2 0
Jitter Frequency, Hz
The accuracy of the XCLK frequency and that of the DJAT PLL reference input
clock used to generate the jitter-free TCLKO have an effect on the minimum jitter
tolerance. For T1 interfaces, the DJAT PLL reference clock accuracy can be
±200 Hz from 1.544 MHz, and the XCLK input accuracy can be ±100 ppm from
37.056 MHz. For E1 interfaces, the PLL reference clock accuracy can be ± 103
Hz from 2.048 MHz, and the XCLK input accuracy can be ±100 ppm from 49.152
MHz. The minimum jitter tolerance for various differences between the
frequency of PLL reference clock and XCLK/24 are shown in Figure 11 and
Figure 12.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
52
PMC [ PMC-SIERRA, INC ]
