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PM7344 参数 Datasheet PDF下载

PM7344图片预览
型号: PM7344
PDF下载: 下载PDF文件 查看货源
内容描述: SATURN QUAD T1 / E1 MULTI -PHY用户网络接口设备 [SATURN QUAD T1/E1 MULTI-PHY USER NETWORK INTERFACE DEVICE]
分类和应用: 网络接口
文件页数/大小: 293 页 / 1101 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7344 S/UNI-MPH  
DATA SHEET  
PMC-950449  
ISSUE 6  
MULTI-PHY USER NETWORK INTERFACE  
9
FUNCTIONAL DESCRIPTION  
Digital Receive Interface (DRIF)  
9.1  
The Digital Receive Interface provides control over the various input options  
available on the multifunctional digital receive pins RDP/RDD and  
RDN/RLCV/ROH. When configured for dual-rail input, the multifunctional pins  
become the RDP and RDN inputs. These inputs can be enabled to receive  
either return-to-zero (RZ) or non-return-to-zero (NRZ) signals; the NRZ input  
signals can be sampled on either the rising or falling edge of RCLKI. When the  
interface is configured for single-rail input, the multifunctional pins become the  
RDD and RLCV inputs, which can be sampled on either the rising or falling  
RCLKI edge. Finally, when the T1/E1 framers are bypassed, the multifunction  
pins become the RDD and ROH inputs, which support arbitrary bit rate interfaces  
such as the 6.312 Mbit J2 rate. The S/UNI-MPH contains internal logic that  
allows it to be interfaced directly to the Transwitch JT2F framer device. A single  
S/UNI-MPH along with four JT2Fs is used to implement a quad J2 user network  
interface.  
Clock and Data Recovery  
The Clock and Data Recovery function is contained in the DRIF block and is  
active when clock recovery is enabled for T1 or E1 interfaces in the dual-rail  
input configuration. The CDRC provides clock and data recovery, B8ZS/HDB3  
decoding, bipolar violation detection, and loss of signal detection. It recovers the  
clock from the incoming RZ data pulses using a digital phase-locked-loop and  
recovers the NRZ data. Loss of signal is declared after exceeding a  
programmed threshold of 10, 31, 63, or 175 consecutive bit periods of the  
absence of pulses on both the positive and negative line pulse inputs and is  
removed after the occurrence of a single line pulse. An alternate loss of signal  
removal criteria requires that minimum pulse density requirements be satisfied  
before loss of signal is removed. If enabled, a microprocessor interrupt is  
generated when a loss of signal is detected and when the signal returns.  
The input jitter tolerance for T1 interfaces complies with the Bellcore Document  
TA-TSY-000170 and with the AT&T specification TR 62411. The tolerance is  
measured with a QRSS sequence (220-1 with 14 zero restriction). The CDRC  
block provides two algorithms for clock recovery that result in differing jitter  
tolerance characteristics. The first algorithm (when the ALGSEL register bit is  
logic 0) provides good low frequency jitter tolerance, but the high frequency  
tolerance is close to the TR 62411 limit. The second algorithm (when ALGSEL is  
logic 1) provides much better high frequency jitter tolerance, approaching  
0.5UIpp (Unit Intervals peak-to-peak), at the expense of the low frequency  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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