PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Pin Name
Type
Pin Function
No.
RXPRTY
Tristate
Output
84
Receive Parity (RXPRTY). This signal indicates
the parity of the RDAT[7:0] bus. Odd or even
parity selection can be made using a register.
RXPRTY is updated on the rising edge of
RFCLK and is tristated when
RRDENB[4:1]/RRDMPHB is high.
RSOC
Tristate
Output
83
Receive Start of Cell (RSOC). This signal marks
the start of cell on the RDAT[7:0] bus. When
RSOC is high, the first octet of the cell is present
on the RDAT[7:0] stream. RSOC is updated on
the rising edge of RFCLK and is tristated when
RRDENB[4:1]/RRDMPHB is high.
RCA[4]
RCA[3]
RCA[2]
RCA[1]
Output
Input
61
60
59
58
Receive Cell Available (RCA[4:1]). These output
signals indicate when a cell is available in the
receive FIFO for the corresponding port.
RCA[4:1] can be configured to be deasserted
when either zero or four bytes remain in the
FIFO. RCA[4:1] will thus transition low on the
rising edge of RFCLK after the 53rd or 48th byte
has been output.
Transmit FIFO Write Clock (TFCLK). This signal
is used to write ATM cells to the four cell
transmit FIFOs. TFCLK cycles at a 25 MHz or
lower instantaneous rate. A complete 53 octet
cell must be written to the FIFO before being
inserted in the transmit stream. Idle/unassigned
cells are inserted when a complete cell is not
available.
TFCLK
38
TDAT[0]
TDAT[1]
TDAT[2]
TDAT[3]
TDAT[4]
TDAT[5]
TDAT[6]
TDAT[7]
Input
66
67
68
69
70
71
72
73
Transmit Cell Data Bus (TDAT[7:0]). This bus
carries the ATM cell octets that are written to the
selected transmit FIFO. TDAT[7:0] is sampled
on the rising edge of TFCLK and is considered
valid only when TWRENB[n]/TWRMPHB is
simultaneously asserted.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
30
PMC [ PMC-SIERRA, INC ]
