欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM7344 参数 Datasheet PDF下载

PM7344图片预览
型号: PM7344
PDF下载: 下载PDF文件 查看货源
内容描述: SATURN QUAD T1 / E1 MULTI -PHY用户网络接口设备 [SATURN QUAD T1/E1 MULTI-PHY USER NETWORK INTERFACE DEVICE]
分类和应用: 网络接口
文件页数/大小: 293 页 / 1101 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7344的Datasheet PDF文件第33页浏览型号PM7344的Datasheet PDF文件第34页浏览型号PM7344的Datasheet PDF文件第35页浏览型号PM7344的Datasheet PDF文件第36页浏览型号PM7344的Datasheet PDF文件第38页浏览型号PM7344的Datasheet PDF文件第39页浏览型号PM7344的Datasheet PDF文件第40页浏览型号PM7344的Datasheet PDF文件第41页  
PM7344 S/UNI-MPH  
DATA SHEET  
PMC-950449  
ISSUE 6  
MULTI-PHY USER NETWORK INTERFACE  
Pin Name  
Type  
Pin Function  
No.  
RDLCLK[4] Output  
RDLCLK[3]  
78  
77  
76  
75  
Receive Data Link Clock (RDLCLK). The  
RDLCLK signal is available on this pin when the  
internal HDLC receiver (RFDL) is disabled from  
use. RDLCLK is used to process the data  
stream contained on RDLSIG. When the S/UNI-  
MPH is configured to receive T1-SF formatted  
data, or when the T1/E1 framers are bypassed,  
RDLCLK is held low. In all other formats the  
rising edge of RDLCLK can be used to sample  
the data on RDLSIG.  
RDLCLK[2]  
RDLCLK[1]/  
RDLEOM[4]  
RDLEOM[3]  
RDLEOM[2]  
RDLEOM[1]  
Receive Data Link End of Message (RDLEOM).  
The RDLEOM signal is available on this pin  
when RFDL is enabled. RDLEOM goes high  
when the last byte of a received sequence is  
read from the RFDL FIFO buffer, or when the  
FIFO buffer is overrun.  
TDLSIG[4]  
TDLSIG[3]  
TDLSIG[2]  
TDLSIG[1]/  
I/O  
42  
41  
40  
39  
Transmit Data Link Signal (TDLSIG). The  
TDLSIG signal is input on this pin when the  
internal HDLC transmitter (XFDL) is disabled  
from use. TDLSIG is the source for the data  
stream to be inserted into the data link. When  
the S/UNI-MPH is configured to transmit T1-ESF  
formatted data, TDLSIG contains the data  
stream inserted in the facility data link; when the  
S/UNI-MPH is configured to transmit T1-SF  
formatted data, TDLSIG is ignored; when the  
S/UNI-MPH is configured to transmit E1  
formatted data, TDLSIG contains the data  
stream inserted in timeslot 16 or a data stream  
inserted in any combination of the national bits.  
TDLSIG is sampled on the rising edge of  
TDLCLK.  
TDLINT[4]  
TDLINT[3]  
TDLINT[2]  
TDLINT[1]  
Transmit Data Link Interrupt (TDLINT). The  
TDLINT signal is output on this pin when XFDL  
is enabled. TDLINT goes high when the last  
data byte written to the XFDL has been set up  
for transmission and processor intervention is  
required to either write control information to end  
the message, or to provide more data.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
21