PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
HCS byte exiting the FIFO is 55H. When FIXPAT is logic 0, the pattern force
in the HCS byte is an alternating AAH/55H pattern which alternate every cell.
LCD:
The LCD bit indicates the state of the Loss of Cell Delineation indication.
When LCD is logic 1, an out of cell delineation (OCD) defect has persisted for
a programmable time (see the RXCP LCD Count Threshold register),
LCDI:
The LCDI bit is set to logic 1 when the state of loss of cell delineation (LCD)
changes. The LCDI bit position is set to logic 0 when this register is read.
LCDE:
The LCDE bit enables the generation of an interrupt when the LCD state
changes. When a logic 1 is written to the LCDE bit position, the interrupt
generation is enabled.
REMPTY4:
The REMPTY4 bit selects the amount of advance indication given on the
receive cell available (RCA) signal. When REMPTY4 is logic 1, RCA is
deasserted when the receive FIFO is almost empty and can accept no more
than four byte read requests before having no more cells available to be read.
When REMPTY4 is logic 0, RCA is deasserted to logic 0 when the receive
FIFO can accept no more read requests (if a read request is made while RCA
is low, the read request is ignored).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
185
PMC [ PMC-SIERRA, INC ]
