PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Registers 038H, 138H, 238H and 338H: RFDL Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
Unused
TR
X
X
X
X
X
X
0
R/W
R/W
EN
0
EN:
The enable bit (EN) controls the overall operation of the RFDL. When set,
the RDFL is enabled; when reset, the RFDL is disabled. When the block is
disabled, the FIFO and interrupts are all cleared; however, the programming
of the Enable/Status Register is not affected. When the block is enabled, it
will immediately begin looking for flags.
TR:
Setting the terminate reception bit (TR) forces the RFDL to immediately
terminate the reception of the current HDLC frame, empty the FIFO, clear the
interrupts, and begin searching for a new flag sequence. The RFDL handles
the TR input in the same manner as if the EN bit had been cleared and then
set. The TR bit in the Configuration register will reset itself after a rising and
falling edge have occurred on the datalink clock input to the RFDL once the
write to this register has completed. If the Configuration register is read after
this time, the TR bit value returned will be zero.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
135
PMC [ PMC-SIERRA, INC ]
