PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Registers 00EH Clock Activity Monitor
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
XCLKIA
RCLKI1A
RCLKI2A
RCLKI3A
RCLKI4A
TCLKIA
0
0
0
0
0
0
0
0
TFCLKA
RFCLKA
This register provides activity monitoring on S/UNI-MPH clock inputs.
XCLKA:
The XCLKA bit monitors for low to high transitions on the XCLK input.
XCLKA is set high on a rising edge of XCLK, and is set low when this register
is read.
RCLKI1A, RCLKI2A, RCLKI3A, RCLKI4A:
The RCLKIxA bits monitors for low to high transitions on the RCLKI[x] inputs.
RCLKIxA is set high on a rising edge of RCLKI[x], and is set low when this
register is read.
TCLKIA:
The TCLKIA bit monitors for low to high transitions on the TCLKI input.
TCLKIA is set high on a rising edge of TCLKI, and is set low when this
register is read.
TFCLKA:
The TFCLKA bit monitors for low to high transitions on the TFCLK input.
TFCLKA is set high on a rising edge of TFCLK, and is set low when this
register is read.
RFCLKA:
The RFCLKA bit monitors for low to high transitions on the RFCLK input.
RFCLKA is set high on a rising edge of RFCLK, and is set low when this
register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
94
PMC [ PMC-SIERRA, INC ]
