PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
14.2.1 Default Application
Upon reset, the S/UNI-MPH default condition provides jitter attenuation with
TCLKO[x] referenced to the transmit clock TCLKI. The DJAT SYNC bit is also
logic 1 by default. DJAT is configured to divide its input clock rate, TCLKI, and its
output clock rate, TCLKO[x], both by 48, which is the maximum length of the
FIFO. These divided down clock rates are then used by the phase comparator to
update the DJAT DPLL. The phase delay between TCLKI and TCLKO[x] is
synchronized to the physical data delay through the FIFO. For example, if the
phase delay between TCLKI and TCLKO[x] is 12UI, the FIFO will be forced to lag
its output data 12 bits from its input data.
The default mode works well with TCLKI at 1.544MHz for T1 operation format or
at 2.048MHz for E1 operation format.
14.2.2 Data Burst Application
In applications where TCLKI works at a higher than nominal instantaneous rate
(but with gapping to provide the same nominal rate over time), a few factors must
be considered to adequately filter the resultant TCLKO[x] into a smooth
1.544MHz or 2.048MHz clock. The magnitude of the phase shifts in the
incoming bursty data are too large to be properly attenuated by the PLL alone.
However, the magnitudes, and the frequency components of these phase shifts
are known, and are most often multiples of 8 kHz.
In this situation, the input clock to DJAT is a gapped bursty clock. The phase
shifts of the input clock with respect to the generated TCLKO[x] in this case are
large, but when viewed over a longer period, such as a frame, there is little net
phase shift. Therefore, by choosing the divisors appropriately, the large phase
shifts can be filtered out, leaving a stable reference for the DPLL to lock onto. In
this application, the N1 and N2 divisors should be changed to C0H (i.e. divisors
of 193 for T1 applications) or FFH (i.e. divisors of 256 for E1 applications).
Consequently, the frequency of the clock inputs to the phase discriminator in the
PLL is 8 kHz. The DJAT SYNC option must be disabled since the divisor
magnitude of 193 or 256 is not an integer multiple of the FIFO length 48.
The self-centering circuitry of the FIFO should be enabled by setting the CENT
register bit. This sets up the FIFO read pointer to be at least 4 UI away from the
end of the FIFO registers, and then disengages. Should variations in the
frequency of input clock or the output clock cause the read pointer to drift to
within one unit interval of FIFO overflow or underflow, the pointer will be
incrementally pushed away by the LIMIT control without any loss of data.
With SYNC disabled, and CENT and LIMIT enabled, the maximum tolerable
phase difference between the bursty input clock and the smooth TCLKO[x] is
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
241
PMC [ PMC-SIERRA, INC ]
