PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
14
OPERATION
Using the Internal FDL Transmitter
Upon reset of the S/UNI-MPH, the XFDL should be disabled by setting the EN bit
in the XFDL Configuration Register to logic 0. If data is not ready to be
transmitted, the TDLINT[x] output should also be masked by setting the INTE bit
to logic 0.
When initializing the XFDL, the XFDL Configuration Register should be set for
transmission: if the FCS is desired, the CRC bit should be set to logic 1; if the
block is to be used in interrupt driven mode, interrupts should be enabled by
setting the INTE bit to logic 1. Finally, the XFDL can be enabled by setting the
EN bit to logic 1. If no message is sent after the EN bit is set to logic 1,
continuous flags will be sent.
The XFDL can be used in a polled, interrupt driven, or DMA-controlled mode for
the transfer of frame data. In the polled mode, the TDLINT[x] and TDLUDR[x]
outputs of the XFDL are not used, and the processor controlling the XFDL must
periodically read the XFDL Interrupt Status Register to determine when to write
to the XFDL Transmit Data Register. In the interrupt driven mode, the processor
controlling the XFDL uses either the TDLINT[x] output, or the main processor
INTB output and the interrupt source registers, to determine when to write to the
XFDL Transmit Data Register. In the DMA controlled mode, the TDLINT[x]
output of the XFDL is used as a DMA request input to the DMA controller, and
the TDLUDR[x] output is used as an interrupt to the processor to allow handling
of exceptions. The TDLUDR[x] output can also be enabled to generate a
processor interrupt through the common INTB output via the TDLUDRE bit in the
Datalink Options register.
Polled Mode
If the XFDL data transfer is operating in the polled mode (TXDMASIG, TDLINTE,
and TDLUDRE bits in the Datalink Options Register are set to logic 0), then a
timer periodically starts up a service routine, which should process data as
follows:
1. Read the XFDL Interrupt Status Register and poll the UDR and INT bits.
2. If UDR=1, then clear the UDR bit in the XFDL Interrupt Status Register to
logic 0, and restart the current frame. Go to step 1.
3. If INT=1, then:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
230
PMC [ PMC-SIERRA, INC ]
