PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
signalling data nibble in the lower four bits of the time slot byte. A logic 0 in
the DLEN bit position is reserved and should not be used.
GENCRC:
The GENCRC bit enables generation of the CRC multiframe. When
GENCRC is a logic 1, the E1-TRAN generates the CRC multiframe alignment
signal, calculates and inserts the CRC bits, and if enabled by FEBEDIS,
inserts the FEBE indication in the spare bit positions. When GENCRC is set
to logic 0, the CRC generation is disabled. The CRC bits are then set to the
logic value contained in the Si[1] bit position in the International/National Bit
Control Register and bit 1 of the NFAS frames are set to the value of Si[0] bit.
FDIS:
The FDIS bit value controls the generation of the framing alignment signal. A
logic 1 in the FDIS bit position disables the generation of the framing pattern
in TS0. A logic 0 in FDIS enables the generation of the framing pattern,
replacing TS0 of frames 0,2,4,6,8,10,12,14 with the frame alignment signal.
When FDIS is a logic 1, framing is globally disabled and the values in controls
bits GENCRC and FEBEDIS are ignored.
Note that the above is true only if the AIS bit in the Transmit Alarm /
Diagnostic Control Register is a logic 0. If AIS is logic 1, the output bit stream
becomes all ones unconditionally.
GENCRC and FEBEDIS:
When FDIS is a logic 0, the bit values used for the International and National
bits are dependent upon the values of the GENCRC and FEBEDIS
configuration bits, as follows:
GENCRC FEBEDIS Source of International/National bits
0
X
Bit Si[1] of the International/National Control
Register is used for the International bit in the
frame alignment signal (FAS) frames and the Si[0]
bit is used for the International bit in the non-frame
alignment signal (NFAS) frames. Bits Sn[4:8] in
the register are used for the National bits in NFAS
frames.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
153
PMC [ PMC-SIERRA, INC ]
