PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Registers 01BH, 11BH, 21BH and 31BH: DJAT Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Reserved
CENT
UNDE
OVRE
X
X
1
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
SYNC
LIMIT
These registers control the operation of the DJAT FIFO read and write pointers
and controls the generation of interrupt by the FIFO status.
Reserved:
This bit should be set to logic 1 for proper operation.
CENT:
The CENT bit allows the FIFO to self-center its read pointer, maintaining the
pointer at least 4 UI away from the FIFO being empty or full. When CENT is
set to logic 1, the FIFO is enabled to self-center for the next 384 transmit data
bit period, and for the first 384 bit periods following an overrun or underrun
event. If an EMPTY or FULL alarm occurs during this 384 UI period, then the
period will be extended by the number of UI that the EMPTY or FULL alarm
persists. During the EMPTY or FULL alarm conditions, data is lost. When
CENT is set to logic 0, the self-centering function is disabled, allowing the
data to pass through uncorrupted during EMPTY or FULL alarm conditions.
The CENT bit can only be set to logic 1 if the SYNC bit in this register is set to
logic 0.
OVRE,UNDE:
The OVRE and UNDE bits control the generation of an interrupt on the
microprocessor INTB pin when a FIFO error event occurs. When OVRE or
UNDE is set to logic 1, an overrun event or underrun event, respectively, is
allowed to generate an interrupt on the INTB pin. When OVRE or UNDE is
set to logic 0, the FIFO error events are disabled from generating an interrupt.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
108
PMC [ PMC-SIERRA, INC ]
