S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
9
Pin Description
Pin Name
SRAM Interface (95 Pins)
The SRAM interface is a 2.5V, 125 MHz ZBT SRAM interface.
Type
Pin No Function
XCLK
Input
Crystal clock, nominally 125 MHz.
SRAMCLK_O
Output
SRAM Clock Out. This clock is derived from XCLK, and must
drive both the SRAM and the SYSCLK input for proper operation.
SYSCLK_O
Output
SYSCLK Output Feedback Clock. This clock is identical to
SRAMCLK_O, but must be connected to the SYSCLK input. It is
used to match the delays that SRAMCLK_O experiences,
allowing the timing on the SRAM interface to be guaranteed.
SYSCLK
Input
I/O
System Clock. This clock must be driven by the SYSCLK_O
output.
SRAM Data. During a write, this output is updated on
SRAMCLK_O. During reads, this input is sampled on the rising
edge of SYSCLK. One cycle of high-impedance is inserted
between changes of direction on this I/O.
SDAT[63:0]
SPAR[7:0]
I/O
SRAM Parity. These bits provide byte parity protection across
SDAT[63:0] and SADDR[17:0]. During writes, SPAR[7:0] is
generated by XORing together 8 bits of odd parity on SDAT[63:0]
with 3 bits, LSB justified, of odd parity on SADDR[17:0]. During
writes, this output is updated on the rising edge of SRAMCLK_O.
During reads, this input is sampled on the rising edge of
SYSCLK. One cycle of high-impedance is inserted between
changes of direction on this I/O.
SADDR[17:0]
Output
SRAM Address. 18 bits are provided, to support up to a 256Kx72
external SRAM. If less SRAM is provisioned, the MSB of the
RAM address (which selects the Linkage vs Search tables)
should still be connected to SADDR[17]; SADDR[16] may be left
unconnected if only 8M of external SRAM is needed,
SADDR[16:15] if only 4M, and so on. This output is updated on
the rising edge of SRAMCLK_O.
SRWB
SCEB
Output
Output
SRAM Read/Write. Indicates whether a read or a write access is
to be executed on the SRAM. Updated on the rising edge of
SRAMCLK_O.
SRAM Chip Enable. When low, activates the external SRAM for
an access. When high, the SRAM is deselected, and must go
high-impedance on the third subsequent rising edge of
SRAMCLK_O. Updated on the rising edge of SRAMCLK_O.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
45
PMC [ PMC-SIERRA, INC ]
