S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Pin Name
Input Cell/Packet Interface (49 Pins)
This interface can work in one of four different modes:
Type
Pin No Function
Mode A (ingress UL3 master input) : Rx Link Layer UTOPIA L3 interface (prefix: RLU_*)
Mode B (egress UL3 slave input) : Tx PHY Layer UTOPIA L3 interface (prefix: TPU_*)
Mode C (PosPhy ingress input) : Rx Link Layer PosPhy L3 interface (prefix: RLP_*)
Mode D (PosPhy egress input) : Tx PHY Layer PosPhy L3 interface (prefix: TPP_*)
One of these four modes may be chosen in software. The choice of mode is static is must not be changed during
chip operation. The easiest way to read the table below is to pick a mode of operation (A,B,C, or D) and to read
only those lines that pertain to the chosen mode.
Each pin also has a generic name, which may be used to reference the pin diagrams.
ICIF_CLK
Input
(A) RLU_CLK
(A) Clock. Valid frequency is 75 to 104 MHz. All signals on this
interface are sampled at the rising edge of this clock. Full OC-
48c bandwidth is guaranteed only for 104 MHz.
(B) TPU_CLK
(C) RLP_CLK
(D) TPP_CLK
(B) Clock. Valid frequency is 75 to 104 MHz. All signals on this
interface are sampled at the rising edge of this clock. Full OC-48c
bandwidth is guaranteed only for 104 MHz.
(C) Clock. Valid frequency is 75 to 104 MHz. All signals on this
interface are sampled at the rising edge of this clock. Full OC-48c
bandwidth is guaranteed only for 104 MHz.
(D) Clock. Valid frequency is 75 to 104 MHz. All signals on this
interface are sampled at the rising edge of this clock. Full OC-48c
bandwidth is guaranteed only for 104 MHz.
ICIF_DAT[31:0]
Input
(A) RLU_DAT[31:0]
(A) 32-bit data bus. The data path for data from the PHY to the
S/UNI-ATLAS-3200. In the 32-bit data path, RLU_DAT[31] is the
MSB, RLU_DAT[0] is the LSB.
(B) TPU_DAT[31:0]
(C) RLP_DAT[31:0]
(B) 32-bit data bus. The data path for data from the Traffic
Manager/Fabric to the S/UNI-ATLAS-3200. In the 32-bit data
path, TPU_DAT[31] is the MSB, TPU_DAT[0] is the LSB.
(C) 32-bit data bus. The RLP_DAT[31:0] bus carries the packet
octets that are read from the receive FIFO and the in-band port
address of the selected receive FIFO. RLP_DAT[31:0] is
considered as valid packet data when RLP_VAL is asserted.
When RLP_EOP is asserted, the RLP_MOD[1:0] bits indicate
how many bytes are valid. When RLP_SX is asserted,
RLP_DAT[7:0] contains the in-band port address, and
RLP_DAT[31:24] optionally carries the Payload Type field
identifying the packet as ATM or POS.
RLP_DAT[31] is the most significant bit.
(D) TPP_DAT[31:0]
(D) 32-bit data bus. This bus carries the packet octets that are
written to the selected transmit FIFO and the in-band port
address to select the desired transmit FIFO. The TPP_DAT bus
is considered valid packet data when TPP_ENB is asserted.
When TPP_SX is asserted, TPP_DAT[7:0] contains the in-band
port address, and TPP_DAT[31:24] optionally carries the Payload
Type field identifying the packet as ATM or POS.
TPP_DAT[31] is the most significant bit.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
46
PMC [ PMC-SIERRA, INC ]
