S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
6
Block Diagram
Figure 3 S/UNI-ATLAS-3200 Block Diagram
125 MHz Pipelined ZBT
SRAM Interface
JTAG
CELL FLOW
JTAG Interface
Packet Bypass
Scalable Data
Queue
Ingress Input:
UL3 master or
POS PHY link
layer interface
(RxLink)
Ingress Output:
UL3 slave or
POS PHY phy
layer interface
(RxPHY)
Cell Processor
Policing, OAM,
UL3/PL3
UL3/PL3
Statistics,
inputs[46:0]
Outputs [46:0]
Translation
ICIF
OCIF
UL3/PL3
UL3/PL3
Egress Input:
UL3 slave or
POS PHY phy
layer interface
(TxPHY)
Egress Input:
UL3 master or
POS PHY link
layer interface
(TxLink)
Connection Table
(Embedded
DRAM)
Outputs [8:0]
Inputs [8:0]
Input
Output
Microprocessor
Cell Interface
(IMCIF)
Microprocessor
Cell Interface
(OMCIF)
Generic Microprocessor
Programming Interface
Input Backwards Cell
Ouput Backwards Cell
Interface (IBCIF)
Interface (OBCIF)
SCI-PHY Rx Master
Intrerface
SCI-PHY Rx Slave
Interface
Microprocessor Interface
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
34
PMC [ PMC-SIERRA, INC ]
