S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Cell rate policing is supported through a dual leaky bucket policer that conforms to the ITU-T
I.371 Generic Cell Rate Algorithm for each connection. Each cell that violates the traffic contract
can be tagged, discarded, or just counted. To allow full flexibility, each GCRA instance can be
programmed to police any combination of user cells, OAM cells, Resource Management cells,
high priority cells or low priority cells. On a per-connection basis, one of eight policing
configurations may be chosen. Three 16-bit non-compliant cell counts are provided on a per-
connection basis. These counters are programmable and allow for the counting of, for example,
dropped CLP0 cells, dropped CLP1 cells and tagged CLP0 cells.
On a per-VC basis, the dual leaky bucket policer may be configured to perform ATM Forum TM
4.1-compliant GFR policing. In this mode, the non-compliant counts may be configured to count
received frames, dropped frames, or tagged frames as well as counting dropped or tagged cells.
The S/UNI-ATLAS-3200 also supports a single leaky bucket policer on a per-PHY basis (up to 48
instances can be programmed). Any or all connections on a particular PHY can be policed by the
PHY GCRA. Each PHY GCRA has a programmable action field that allows violating cells to be
tagged, discarded, or just counted. Three configurable non-compliant cell counts (on each PHY
GCRA) are also provided. Each PHY GCRA can be programmed to police any combination of
user cells, OAM cells, Resource Management cells, high priority cells or low priority cells. Any
one of four PHY policing configurations may be chosen.
The 32-bit Microprocessor Interface is provided for device configuration, control and monitoring
by an external microprocessor. This interface provides access to the external SRAM and internal
DRAM to allow creation of the data structure, configuration of individual connections, and
monitoring of the connections. The Microprocessor Cell FIFO permits insertion and extraction of
cells. Programmed cell types can be routed to the Microprocessor Cell FIFO (and subsequently
read through the Microprocessor cell interface). The microprocessor may insert cells into the cell
stream which may be processed, translated, counted, routed, and policed by the S/UNI-ATLAS-
3200, or not, at the option of the microprocessor.
When the device is in Egress mode, the Output Cell Interface is a 32-bit UTOPIA Level 3 or
POS-PHY Level 3 transmit Link Layer interface which can address up to 48 PHY queues on a
PHY device using polled addressing. Cells are stored in a per-PHY programmable-depth FIFO
and subsequently transferred to a PHY device. A total of 192 cell buffers are provided, which
may be divided up among the PHYs as desired. A PHY output buffer requires at least 12 cell
buffers if it is to maintain full STS-12 or more on that PHY, 4 cell buffers if it is to maintain STS-
3 on that PHY, and 2 cell buffers if it is to maintain STS-1 or less on that PHY. The FIFO depth
for each PHY can be configured to hold 2, 4, 12, or 48 cells.
When the device is in Ingress UL3 mode, the Output Cell Interface is a 32-bit UTOPIA Level 3
Rx PHY (Slave) interface which may mimic up to 48 PHYs using polled addressing, or may
optionally operate without polling. When configured in Ingress POS-PHY mode, the Output Cell
Interface is a POS-PHY Level 3 Rx PHY Layer which mimics up to 48 PHYs. Cells are stored in
a per-PHY programmable-depth FIFO and subsequently transferred to a TM or switch device. A
total of 192 cell buffers are provided, which may be divided up among the PHYs as desired. A
PHY output buffer requires at least 12 cell buffers if it is to maintain full STS-12 or more on that
PHY, 4 cell buffers if it is to maintain STS-3 on that PHY, and 2 cell buffers if it is to maintain
STS-1 or less on that PHY. The FIFO depth for each PHY can be configured to hold 2, 4, 12, or
48 cells.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
36
PMC [ PMC-SIERRA, INC ]
