PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
Unstructured data is received without regard to the byte alignment of data within a frame and is
placed in the frame buffer in the order in which it arrives. Figure 13 shows the basic components
of the TFTC.
Line 0
Line 0
ATTN0
DATA0
3
External
Framer
Receive Line
Interface
Line Encoder
Line Number
ANY
•
•
•
•
•
•
4
16
Channel Pair Number
Line-to-Memory
Interface
Line 7
Line 7
ATTN7
DATA7
External
Framer
Receive Line
Interface
16
16
Data
Figure 13. Transmit Frame Transfer Controller
The receive line interface is primarily a serial-to-parallel converter. Serial data, which is derived
from the RL_SER pin, is supplied to a shift register. The shift register clock is the RL_CLK input
from the external framer. When the data has been properly shifted in, it is transferred to a 2-byte
holding register by an internally derived channel clock. This clock is derived from the line clock
and the framing information.
The channel clock also informs the line-to-memory interface that two data bytes are available
from the line. When the two bytes are available, a line attention signal is sent to the line encoder
block. However, because the channel clock is an asynchronous input to the line-to-memory inter-
face, it is passed through a synchronizer before it is supplied to the line encoder. Since there are
eight potential lines and each of them provides its own channel clock, they are synchronized
before being submitted to the line encoder.
The TFTC accommodates the T1 Super Frame (SF) mode by treating it like the Extended Super
Frame (ESF) format. The TFTC ignores every other frame pulse and captures signaling data only
on the last frame of odd SF multiframes. The formatting of data in the signaling buffers is highly
dependent on the operating mode. Refer to section 7.6.6 “RESERVED (Transmit Signaling
Buffer)” on page 132 for more information on the transmit signaling buffer.
ꢁꢆ
PMC [ PMC-SIERRA, INC ]
