PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
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AAL1 SAR Processor
3 THEORY OF OPERATIONS
The AAL1gator II is divided into the following major blocks, all of which are explained in this
section:
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•
•
•
•
•
•
•
Transmit Frame Transfer Controller (TFTC) block
Cell Service Decision (CSD) block
Transmit Adaptation Layer Processor (TALP) block
Transmit UTOPIA Interface (TUTOPIA) block
Memory Interface and Arbitration Controller (MIAC) block
Receive Frame Transfer Controller (RFTC) block
Receive Adaptation Layer Processor (RALP) block
Receive UTOPIA Interface (RUTOPIA) block
Figure 10 shows a block diagram of the AAL1gator II and the sequence of events used to segment
and reassemble the CBR data.
AAL1gator II
(PM73121)
Cell Service
Decision
(CSD)
4
2
3
Transmit
Frame
Transfer
Controller
(TFTC)
Transmit
UTOPIA
Interface
Block
Transmit
Adaptation
Layer
Processor
(TALP)
Output to UTOPIA
Input from Line
(TUTOPIA)
1
5
6
Memory
Interface and
Arbitration
Controller
(MIAC)
10
To External Memory
Receive
UTOPIA
Interface
Block
Receive
Frame
Transfer
Controller
(RFTC)
Receive
Adaptation
Layer
Processor
(RALP)
Input from UTOPIA
Output to Line
(RUTOPIA)
7
8
9
Microprocessor
Control Bus
Figure 10. AAL1gator II Block Diagram
1. TFTC stores line data into the memory, 16 bits at a time.
2. When the TFTC finishes writing a complete frame into the memory, it notifies the CSD of a
ꢁꢃ
PMC [ PMC-SIERRA, INC ]
