PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
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Supports Synchronous Residual Time Stamp (SRTS) for unstructured data formats. The
transmit interface generates the 4-bit SRTS code that reflects the difference between the
network clock and the transmitting service clock. If enabled, this SRTS code is inserted
into the Convergence Sublayer Indication (CSI) bit of cells with odd sequence numbers.
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Provides data and signaling conditioning on a per-VC basis.
Provides a 2-cell UTOPIA First-In, First-Out (FIFO).
Transmit delay is defined by the following three components: the time to schedule a cell,
the time to build a cell, and the time to transmit a cell. The time to schedule a cell is from
0 to 125 µs for structured data and from 0 to 256 bit times for unstructured data. The time
(in seconds) to build a cell with a full payload is approximately 376 divided by the CBR
(in bps). The time to send a cell depends on the number of cells queued for transmission,
the amount of OAM traffic being inserted by the microprocessor, and the speed at which
cells are accepted by the device connected to the UTOPIA transmitter. Once the payload is
available, each cell takes about 8.5 µs to prepare.
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Provides optionally generated transmit line clock based on received SRTS values, looped
RL_CLK, or synthesized nominal clock.
2.4 Receive Interface Features
When cells arrive, the AAL1gator II places them in a multiframe buffer based on the channel allo-
cation. The cells are then transmitted to the line interface at the proper time. Other receive inter-
face features include:
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Provides a 33 MHz ATM or PHY layer UTOPIA interface. The PHY side can be either
SPHY or MPHY.
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Provides per-VC queues.
Provides a 0 to 64 ms receive buffer for E1 (0 to 48 ms if using T1 signaling), a 0 to 48 ms
receive buffer for T1, a 0 to 4 ms receive buffer for E3, and a 0 to 2.9 ms receive buffer for
DS3.
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Provides a 0 to 32 ms per-VC Cell Delay Variation Tolerance (CDVT) setting for E1 (0 to
24 ms if using T1 signaling); provides a 0 to 24 ms per-VC CDVT setting for T1 in
increments of 125 µs.
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Provides a 0 to 2 ms CDVT setting for E3 and a 0 to 1.5 ms CDVT setting for DS3.
Provides overrun and underrun protection.
Provides pointer misalignment protection.
Receives, verifies, and corrects sequence numbers in accordance with ITU-T
Recommendation I.363.1. (refer to Appendix B, “References”, on page 203).
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Processes sequence numbers in accordance with I.363.1 “Fast SN Algorithm” (refer to
Appendix B, “References”, on page 203). Sequence number processing can optionally be
disabled on a per queue basis.
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PMC [ PMC-SIERRA, INC ]
