PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
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Allows the outgoing Virtual Path Identifier (VPI)/Virtual Channel Identifier (VCI) to be
set to any value for each VC.
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Maps a selectable 8-bit field of the VCI into 256 possible receive queues.
Provides bit count integrity by replacing lost AAL Service Data Units (SDUs).
Allows any combination of timeslots within one T1/E1 line to be mapped to a VCI.
Supports UDF at arbitrary bit rates up to 20 Mbit/s aggregate throughput.
Provides a per-line CCS/CAS configuration option.
Individual lines can be configured as E1 or T1.
E1 lines can be configured to use T1 signaling rates.
Provides transmit data and signaling conditioning per VC.
Provides receive signaling freezing on underrun, overrun, and pointer mismatch and
errored cells.
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Provides receive data and signaling conditioning per VC.
Provides SRTS bit generation and collection for an internal clock synthesizer to drive
external receive PLLs for unstructured data formats.
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Provides a 16-bit microprocessor interface to a 128K × 16 SRAM external to the device.
Provides statistics and interrupts for the microprocessor.
2.3 Transmit Interface Features
The AAL1gator II accepts deframed data as a serial bit stream from multiple external deframer
devices. The AAL1gator II then stores the data in an external SRAM, and creates AAL1 ATM
cells from the data. The AAL1gator II allows configurations of up to 256 VCs (32 per line) that
can transmit from 1 to 32 DS0s (64 Kbit/s channels) within any one T1 or E1 line with arbitrary
sequential mapping (including alternating timeslots). The VC queues are serviced with a calendar
scheduling mechanism. The transmit side transmit queue controller also supports the transmission
of cells generated by the microprocessor. In addition, a variety of statistics are maintained in
16-bit counters. Other transmit interface features include:
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Provides per-VC transmit queuing.
Provides a calendar queue service algorithm that produces minimal CDV.
Provides a 33 MHz ATM or PHY layer UTOPIA interface. The PHY side can be either
SPHY or MPHY.
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Provides a supervisory transmit buffer for OAM/signaling with Cyclic Redundancy
Check-10 (CRC-10) generation.
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Generates sequence numbers and sequence number protection bits.
Provides partially filled cells with lengths configured on a per-VC basis.
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PMC [ PMC-SIERRA, INC ]
