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PM73121-RI 参数 Datasheet PDF下载

PM73121-RI图片预览
型号: PM73121-RI
PDF下载: 下载PDF文件 查看货源
内容描述: AAL1分段重组处理器 [AAL1 Segmentation And Reassembly Processor]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 223 页 / 2148 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM73121AAL1gator II  
Data Sheet  
PMC-Sierra, Inc.  
PMC-980620  
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AAL1 SAR Processor  
Field (Bits)  
Description  
CSD_ATTN  
(4)  
When written with a 1, causes the device to “OR” the T_ADD_QUEUE table with the  
first entry in the calendar queue, thereby starting up VCs. Resets to 0. Reads as 0 when  
the operation is complete. This operation normally takes up to 3 ms, but is blocked if the  
TALP is not allowed to build new cells. In the presence of severe backpressure at the  
transmit UTOPIA port, the CSD_ATTN bit may not clear.  
CMD_REG_ATTN  
(3)  
When written with a 1, causes the device to write the device revision code into the  
DEVICE_REV location, read the COMP_LIN_REG location, and finally read the eight  
LIN_STR_MODE locations. Reads as a 0 when the operation is complete. Resets to 0.  
SEND_OAM_1  
(2)  
A write of 1 causes the cell in the TX OAM buffer 1 to be sent. Reads as a 0 when the  
cell has been sent. Resets to 0.  
SEND_OAM_0  
(1)  
A write of 1 causes the cell in the TX OAM buffer 0 to be sent. Reads as a 0 when the  
cell has been sent. Resets to 0.  
OAM_INT_MASK  
(0)  
When set, disables the OAM receive interrupt. Resets to 1.  
NOTES:  
SEND_OAM _0 has a higher priority than SEND_OAM_1. Therefore, if the correct  
order of OAM cell transmission is important, both bits should not be set at the same  
time. After SEND_OAM_0 is requested to be sent, the software can build the second  
cell in memory, but should not set the SEND_OAM_1 bit until it has detected that the  
SEND_OAM_0 bit has been cleared.  
Both attention bits (CSD_ATTN and CMD_REG_ATTN) cannot be set simulta-  
neously.  
Dual port RAM testing is enabled when the PROC_TEST_ACCESS bit is asserted. All processor  
accesses will then be directed to the internal RAMs. Address bits 6:0 are used to provide the  
address for the write port and bits 13:7 are used to provide the address for the read port. Bit 15 and  
14 select the respective RAM based upon the following code.  
Bits (15:14)  
Description  
00  
01  
10  
11  
Not used.  
Signal data FIFO.  
Receive FIFO.  
Transmit FIFO.  
7.10 Activating a New Line After Reset  
The microprocessor can activate or deactivate a new line at any time without affecting lines  
already in service. The microprocessor should change the line and then set the line CMD_REG_  
ATTN bit in the microprocessor attention register, informing the AAL1gator II that it must  
interrogate the memory for line status changes. After the requested change has been performed,  
the AAL1gator II clears the attention bit. The microprocessor must not request another change  
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