PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
R_DATA_BUFFER_n Word Format
Field (Bits)
Description
R_DATA_H
(15:8)
Receive data for:
Channel = (offset mod 16) × 2 + 1.
E1 frame = (offset mod 256) ÷ 16.
T1 frame = (offset mod 512) ÷ 16.
E1 multiframe = (offset mod 8192) ÷ 256.
T1 multiframe = (offset mod 8192) ÷ 512.
Line = offset ÷ 8192.
E1 offset = line × 8192 + multiframe(E1) × 256 + frame(E1) × 16 + (chan-1) ÷ 2.
T1 offset = line × 8192 + multiframe(T1) × 512 + frame(T1) × 16 + (chan-1) ÷ 2.
R_DATA_L
(7:0)
Receive data for:
Channel = (offset mod 16) × 2.
E1 frame = (offset mod 256) ÷ 16.
T1 frame = (offset mod 512) ÷ 16.
E1 multiframe = (offset mod 8192) ÷ 256.
T1 multiframe = (offset mod 8192) ÷ 512.
Line = offset ÷ 8192.
E1 offset = line × 8192 + multiframe(E1) × 256 + frame(E1) × 16 + channel ÷ 2.
T1 offset = line × 8192 + multiframe(T1) × 512 + frame(T1) × 16 + channel ÷ 2.
7.9 CMDREG (Command Register)
Organization: 1 register
Base address: 20000h
Index: 1h
Type: Read/Write
Hardware Reset Value: xx21h
Function: Allows the microprocessor to signal events to the AAL1gator II.
Format: Refer to the following table.
CMDREG Word Format
Field (Bits)
Description
Not used
(15:8)
Write with a 0 to maintain compatibility with future software versions.
(Reserved)
PROC_TEST_ACCESS
(7)
Initialize to 0.
When set, destructively allows access to the internal FIFOs for testing purposes. The
device should be reset with either the /RESET pin or the SW_RESET register after this
operation is performed. For production test use only.
CLR_RX_OAM_LATCH
(6)
When set, causes the receive OAM interrupt latch to be cleared. On read:
1 means an OAM interrupt is present.
0 means an OAM interrupt is not present.
SW_RESET
(5)
When set, causes all of the device except the microprocessor interface to be held in reset.
While set, the external SRAM may be accessed. When switching to or from UDF-HS
mode, this bit must be asserted. Resets to 1.
ꢀꢅꢄ
PMC [ PMC-SIERRA, INC ]
