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PM73121-RI 参数 Datasheet PDF下载

PM73121-RI图片预览
型号: PM73121-RI
PDF下载: 下载PDF文件 查看货源
内容描述: AAL1分段重组处理器 [AAL1 Segmentation And Reassembly Processor]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 223 页 / 2148 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM73121AAL1gator II  
Data Sheet  
PMC-Sierra, Inc.  
PMC-980620  
,VVXHꢀꢁ  
AAL1 SAR Processor  
7.6.8 T_QUEUE_TBL  
Organization: 256 × 32 words  
Base address: 2000h  
Index: 20h  
Type: Read/Write  
Function: Configures the VCs.  
Format: Each queue will be allocated 32 consecutive words.  
Offset  
Name  
Description  
(Data pointer.) Initialize to FFFF each time this queue is initialized.  
0h  
1h  
Reserved  
Not used  
Initialize to 0 each time this queue is initialized to maintain future software  
compatibility.  
2h  
3h  
T_COND_CELL_CNT  
A 16-bit rollover count of conditioned cells transmitted.  
T_SUPPRESSED_CELL_CNT  
A 16-bit rollover count of cells not sent because of a line resynchronization. Or,  
if in UDF-HS mode, a 16-bit rollover count of cells not sent because TX_  
ACTIVE is not set. This counter also counts when cells are not sent because  
SUPPRESS_TRANSMISSION is set.  
4h  
Not used  
Initialize to 0 each time this queue is initialized to maintain future software  
compatibility.  
5h  
6h  
7h  
8h  
9h  
Ah  
Bh  
Reserved  
(Sequence number.) Initialize to 0 each time this queue is initialized.  
The configuration of the current queue. Initialize to the proper value.  
A 16-bit count of the cells transmitted.  
QUEUE_CONFIG  
T_CELL_CNT  
TX_HEAD(2:1)  
TX_HEAD(4:3)  
TX_HEAD(5)  
QUE_CREDITS  
Header byte 1 in bits 15:8, header byte 2 in bits 7:0.  
Header byte 3 in bits 15:8, header byte 4 in bits 7:0.  
Header byte 5 (pre-calculated HEC) in bits 15:8.  
A 10-bit quantity representing the number of byte credits accumulated for the  
queue.  
Ch  
Dh  
Eh  
Fh  
CSD_CONFIG  
Stores the average number of bytes in each cell, and carries the number of DS0s  
for this queue.  
Not used  
Initialize to 0 each time this queue is initialized to maintain future software  
compatibility.  
T_CHAN_ALLOC(15:0)  
T_CHAN_ALLOC(31:16)  
A bit table with a bit set per DS0 allocated to this queue for DS0s 15:0 on the line  
defined by queue ÷ 32.  
A bit table with a bit set per DS0 allocated to this queue for DS0s 31:16 on the  
line defined by queue ÷ 32.  
10h  
11h  
12h  
T_CHAN_LEFT(15:0)  
T_CHAN_LEFT(31:16)  
IDLE_CONFIG  
Initialize to the same value as T_CHAN_ALLOC(15:0).  
Initialize to the same value as T_CHAN_ALLOC(31:16).  
Controls transmission of data.  
13h-1Fh Not used  
Initialize to 0 each time this queue is initialized.  
NOTE: All registers are right justified, with any unused bits set to 0.  
ꢀꢂꢃ  
 
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