PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Pin Name Type
Pin No.
Function
PQFP PLCC
35 40
RDLSIG/
Output
Receive Data Link Signal (RDLSIG).
The RDLSIG signal is available on this
output when the internal HDLC
receiver (RFDL) is disabled from use.
RDLSIG contains the data link stream
extracted from the selected data link
bits. The E1XC may be configured to
utilize timeslot 16 as a data link or
utilize any combination of the national
bits as a data link. RDLSIG is
updated on the falling edge of
RDLCLK.
RDLINT
Receive Data Link Interrupt (RDLINT).
The RDLINT signal is available on this
output when RFDL is enabled.
RDLINT goes high when an event
occurs which changes the status of
the HDLC receiver.
RDLCLK/ Output
34
39
Receive Data Link Clock (RDLCLK).
The RDLCLK signal is available on
this output when the internal HDLC
receiver (RFDL) is disabled from use.
RDLCLK is used to process the data
stream contained on the RDLSIG
output. When the E1XC is not
configured to extract a data link, the
RDLCLK output is held low. In all
other formats the rising edge of
RDLCLK can be used to sample the
data on RDLSIG.
RDLEOM
Receive Data Link End of Message
(RDLEOM). The RDLEOM signal is
available on this output when RFDL is
enabled. RDLEOM goes high when
the last byte of a received sequence is
read from the RFDL FIFO buffer, or
when the FIFO buffer is overrun.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
21
PMC [ PMC-SIERRA, INC ]
