PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Table 21
Symbol
- XCLK=49.152MHz Input (Figure 39)
Description
Min
8
Max
Units
ns
t
t
XCLK Low Pulse Width (note 1)
XCLK High Pulse Width (note 1)
L
XCLK
8
ns
H
XCLK
tXCLK
XCLK Period (typically 1/49.152 MHz or 20
20.4 ns)
ns
XCLK Duty Cycle (note 2)
40
4
60
%
t REF
L
REF Low Pulse Width (notes 1,3)
tXCLK
t REF
REF High Pulse Width (notes 1,3)
4
8
tXCLK
H
t
REF Period
tXCLK
REF
Figure 39
- XCLK=49.152MHz InputTiming
tH
XCLK or REF
t
tL
Notes on XCLK=49.152MHzTiming:
1. Input Clock high pulse width is measured from the 1.4 Volt points of the rise
and fall ramps. Low pulse width is measured from the 1.4 Volt points of the
rise and fall ramps.
2.
3. Duty cycle is measured at the 50% points of the rise and fall ramps.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
237
PMC [ PMC-SIERRA, INC ]
