PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 5CH: RSLC Block Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
Unused
Unused
THS
X
X
X
X
X
X
X
0
R/W
THS:
The bit THS controls the selection of slicing threshold. The analog pulse
slicer generates a logic one on either the SDP or SDN output if the amplitude
(positive or negative) of the line voltage exceeds the adaptive slicing
threshold. The THS bit selects between two fractions of the pulse amplitude
for the slicing threshold.
When THS is set to logic 0, the slicing threshold is 67% of the peak
amplitude.
When THS is set to logic 1, the slicing threshold is 50% of the peak amplitude
and is intended for G.703 2048 kbit/s applications.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
183
PMC [ PMC-SIERRA, INC ]
