PMC-Sierra, Inc.
STANDARD PRODUCT
PM5945 -UTP5
PMC-940202 ISSUE 2. APRIL 7, 1995
APP_SAPI_UTP5
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receive PAL will start clocking the data from the S/UNI into the FIFO by generating
the RRDB clock signal. The RSOC signal from the S/UNI is inserted into bit 9 of the
FIFO data inputs. The FIFO enables the /FF (active low FIFO Full) signal when it is
full which disables further transfer of data from the S/UNI to the FIFO. If the FIFO
gets full, the S/UNI will have transferred an indeterminate portion of a cell. The rest
of the cell will get transferred as soon as the FIFO de-activates the /FF signal. The
Receive PAL uses the RxCLK signal from the ATM layer to generate the WClk signal
going to the FIFO and the RRDB clock signal to the S/UNI. The WEN going to the
FIFO is disabled while the /FF is active (low). While the FIFO write enable is
disabled, the clock going to the FIFO is the same as the RxCLK. This is done
because the FIFO /FF signal will not be disabled (high) untill it gets a rising edge on
the WCLK input.
The RxEmptyB signal comes from the Receive FIFO /EF (active low Empty FIFO)
signal. The Receive FIFO de-asserts the the RxEmptyB signal (high) upon reception
of a single byte of data. On the next rising edge of the RxClk clock signal, the ATM
layer samples the RxEmptyB signal and on the following RxClk clock signal, the
ATM layer activates the RxEnbB signal (low) if it has an empty cell available. The
RxEnbB signal from the ATM layer goes to the Receive PAL (U16) and to the read
enable (/RDEN1) input of the receive FIFO. On the next rising edge of the RxCLK
signal after the RxEnbB signal goes active (low) the first byte of data is clocked out of
the FIFO along with the RSOC signal. The receive ATM layer ignores the data until it
sees a valid RSOC signal. Once cell transfer has commenced, the ATM layer
expects a complete cell transfer. If the FIFO is empty (RxEmptyB is active) and then
the S/UNI starts to transfer data to the FIFO, there might only be one byte in the FIFO
before the RxEmptyB signal could go inactive (high). For the FIFO to become empty,
the S/UNI must not have had any cells to transfer and therefore the first byte in the
FIFO would be the first byte of the Cell along with the valid RSOC signal. Since the
RxClk clock signal is generating the write and read clock signals to the FIFO as well
as the read clock signal to the S/UNI, the ATM layer cannot read the data out of the
FIFO faster than the S/UNI can write the data into the FIFO.
SAPI Board Edge Connector Interface
The SAPI UTOPIA Edge Connector Interface includes all the signals required to
connect the SAPI board to a high layer protocol entity (i.e. a AAL processor). Cells
can be written to the S/UNI transmit FIFO and read from the S/UNI receive FIFO
using this interface. The edge connector is made up of a 100 pin dual line female
connector is shown in table below. It consists of signals appropriate to read and
write to the registers of the devices on the daughter board, and it provides the
necessary power and ground. TTL signal levels are used on this interface.
Table 7: Edge Connector Pin Description
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PMC [ PMC-SIERRA, INC ]
