PMC-Sierra, Inc.
STANDARD PRODUCT
PM5945 -UTP5
PMC-940202 ISSUE 2. APRIL 7, 1995
APP_SAPI_UTP5
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the PHY layer is ready to accept a cell of data before the ATM layer is ready to send
data.
The case where the ATM layer has a cell available for transmission before the PHY
layer is ready to accept the cell is handled as follows; The Vicksburg card drives the
TSOC signal active (high) and the TxData bus with valid octet byte zero coincident
with the assertion of the TxClavB signal, and waits for the TxFullB signal from the
PHY layer to go inactive (high). When the PHY device has a cell available, the
TxFullB signal goes inactive (high) and then the TxEnbB signal is immediately
asserted (low) (after a delay through a gate). On the next rising edge of the TxClk
signal, the second byte of data is driven onto the TxData bus and the TSOC signal is
de-asserted (low).
The case where the PHY layer is ready to accept a cell of data before the ATM layer
is ready to transmit the cell is handled as follows; The PHY layer de-asserts the
TxFullB signal (high) and waits for the TxEnbB signal to go active (low). When the
ATM layer has a cell available for transmission, the TxClavB is set active (low) on
the rising edge of the TxClk signal, and drives the TSOC signal active (high) and the
TxData bus with valid octet byte zero . The TxClavB signal sets the TxEnbB signal
active (low) through a gate delay.
In either case, the TxData bus is continually clocked into the first buffer (U18) by the
rising edges of the TxClk signal. The assertion of the TxEnbB signal enables the
TWRB signal to the S/UNI device. On the falling edge of the TWRB signal (rising
edge of TxClk) the data from U18 is clocked into the second buffer (U19). The clock
signal to U19 is generated by the PAL (inverted TxClk). The ATM layer updates the
TxData with new data on the rising edge of each TxClk signal while TxEnbB is
asserted and the TxFullB signal is de-asserted (high). If at the end of the current cell
transfer, another cell is available (TCA remains active), the TxFullB will still be
asserted (low) on the 51'st byte transferred. This is to accomodate the propagation
delay of TCA going inactive (low) at the end of a cell transfer and then being
sampled by the PAL (TCA must be sampled as it can go active at any time). This will
incur an extra clock delay per cell transfer. The TxClavB signal goes inactive (high)
for a minimum of two cycles per cell trasfer. There will be a 3 clock cycle delay per
cell transfer as the TxFullB and the TxClavB overlap.
The Receive drop side interface is controlled by the ATM layer through the edge
connector. All the receive signals from the ATM layer change with respect to the
RxClk. All the input signals to the ATM layer are sampled on the rising edge of the
RxClk. The receive side incorporates a external FIFO so that the S/UNI device does
not overrun due to the latency times between burst cell reads of the ATM layer
(Vicksburg mother board).
The S/UNI device asserts the RCA signal when it has a complete cell to transfer to
the FIFO. The RCA signal goes to the Receive PAL (U16) and the PAL asserts the
write enables to the receive FIFO. If the receive FIFO is not full (/FF high), the
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