PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
10
FUNCTIONAL DESCRIPTION
10.1 Receive Line Interface
The Receive Line Interface allows direct interface of the S/UNI-2488 to optical modules (ODLs) or
other medium interfaces. This block performs clock and data recovery on the incoming 2488.32
Mbit/s data stream and SONET A1/A2 pattern framing.
The clock recovery unit recovers the clock from the incoming bit serial data stream and is
compliant with SONET and SDH jitter tolerance requirements. The clock recovery unit utilizes a
low frequency reference clock to train and monitor its clock recovery PLL. Under loss of signal
conditions, the clock recovery unit continues to output a line rate clock that is locked to this
reference for keep alive purposes. The clock recovery unit utilizes a 155.52 MHz reference clock.
The clock recovery unit provides status bits that indicate whether it is locked to data or the
reference and also supports diagnostic loopback and a loss of signal input that squelches normal
input data.
Initially upon start-up, the PLL locks to the reference clock, REFCLK. When the frequency of the
recovered clock is within TBD ppm of the reference clock, the PLL attempts to lock to the data.
Once in data lock, the PLL reverts to the reference clock if no data transitions occur in TBD bit
periods or if the recovered clock drifts beyond TBD ppm of the reference clock.
When the transmit clock is derived from the recovered clock (loop timing), the accuracy of the
transmit clock is directly related to the REFCLK reference accuracy in the case of a loss of signal
condition. To meet the Bellcore GR-253-CORE SONET Network Element free-run accuracy
specification, the reference must be within +/- TBD ppm. When not loop timed, the REFCLK
accuracy may be relaxed to +/- TBD ppm.
The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the
minimum transition density expected in a received SONET data signal. The total loop dynamics of
the clock recovery PLL yield a jitter tolerance that exceeds the minimum tolerance specified for
SONET equipment by GR-253-CORE. Please refer to the figure below.
Figure 7: Typical STS-48c (STM-16c) Jitter Tolerance
TBD
The Serial to Parallel Converter converts the received bit serial stream to a 16 bit word serial
stream.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
50
PMC [ PMC-SIERRA, INC ]
