PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
Notes on Microprocessor Interface Write Timing:
1
2
A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
In non-multiplexed address/data bus architectures, ALE should be held high so parameters
tS , tH , tV , tS , and tH are not applicable.
ALW ALW LW LW
L
3
4
Parameter tH is not applicable if address latching is used.
AW
When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
5
When a hold time is specified between an input and a clock, the hold time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
456
PMC [ PMC-SIERRA, INC ]
