PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
Figure 26: Intel Microprocessor Interface Read Timing
tSar
tHar
A[13:0]
tSalr
tVl
tHalr
ALE
(CSB+RDB)
INTB
tSlr
tHlr
tZinth
tPrd
tZrd
VALID
D[15:0]
Notes on Microprocessor Interface Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the
reference signal to the 1.4 Volt point of the output.
2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor
Interface data bus, (D[15:0]).
3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
4. In non-multiplexed address/data bus architectures, ALE should be held high so parameters
tS
ALR
, tH
, tV , tS , and tH are not applicable.
ALR
L
LR LR
5. Parameter tH
AR
is not applicable if address latching is used.
6. When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
7. When a hold time is specified between an input and a clock, the hold time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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454
PMC [ PMC-SIERRA, INC ]
