PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
0100
0101
1000
1001
1010
1011
Monitor - Monitor error count page
Monitor - Received B1 and E1
Generator - Timeslot Configuration page
Generator - PRBS[22:7] page
Generator - PRBS[6:0] page
Generator - B1/E1 value page
RWB:
The active high read and active low write (RWB) bit selects if the current access to the
internal register is an indirect read or an indirect write. Writing to the Indirect Address
Register initiates an access to the internal register. When RWB is set to logic 1, an indirect
read access to the register is initiated. The data from the addressed location in the internal
register will be transfer to the Indirect Data Register. When RWB is set to logic 0, an indirect
write access to the register is initiated. The data from the Indirect Data Register will be
transfer to the addressed location in the internal register.
BUSY:
The active high RAM busy (BUSY) bit reports if a previously initiated indirect access to the
internal register has been completed. BUSY is set to logic 1 upon writing to the Indirect
Address Register. BUSY is set to logic 0, upon completion of the RAM access. This register
should be polled to determine when new data is available in the Indirect Data Register.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
383
PMC [ PMC-SIERRA, INC ]
