PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
10.7 RECEIVE CELL AND FRAME PROCESSOR (RCFP)..............................................................................65
10.8 RECEIVE SCALABLE DATA QUEUE (RXSDQ).....................................................................................70
10.9 RECEIVE PHY INTERFACE (RXPHY).................................................................................................71
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
10.19
10.20
10.21
10.22
10.23
TRANSMIT LINE INTERFACE ..........................................................................................................71
SONET/SDH TRANSMIT LINE INTERFACE (STLI)..........................................................................72
TRANSMIT REGENERATOR MULTIPLEXOR PROCESSOR (TRMP).....................................................72
TRANSMIT TAIL TRACE PROCESSOR (TTTP).................................................................................75
TRANSMIT HIGH ORDER PATH PROCESSOR (THPP)......................................................................76
TRANSMIT CELL AND FRAME PROCESSOR (TCFP) ........................................................................76
TRANSMIT SCALABLE DATA QUEUE (TXSDQ) ...............................................................................79
TRANSMIT PHY INTERFACES (RXPHY AND TXPHY) .....................................................................79
SONET/SDH BIT ERROR RATE MONITOR (SBER).......................................................................80
SONET/SDH ALARM REPORTING CONTROLLER (SARC) .............................................................80
SONET/SDH INBAND ERROR REPORT PROCESSOR (SIRP).........................................................81
APS SERIAL DATA INTERFACE......................................................................................................82
JTAG TEST ACCESS PORT INTERFACE .........................................................................................83
MICROPROCESSOR INTERFACE.....................................................................................................83
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NORMAL MODE REGISTER DESCRIPTION.................................................................................97
OPERATION...................................................................................................................................430
12.2 SONET/SDH FRAME MAPPINGS AND OVERHEAD BYTE USAGE ......................................................433
12.3 POS/HDLC DATA STRUCTURE......................................................................................................438
12.4 SETTING ATM MODE OF OPERATION..............................................................................................439
12.5 SETTING PACKET OVER SONET/SDH MODE OF OPERATION .........................................................439
12.6 BIT ERROR RATE MONITOR............................................................................................................439
12.7 CLOCKING OPERATIONS ................................................................................................................439
12.8 LOOPBACK OPERATION..................................................................................................................439
12.9 BOARD DESIGN RECOMMENDATIONS..............................................................................................440
12.10
12.11
POWER SUPPLIES......................................................................................................................440
INTERFACING TO ECL OR PECL DEVICES...................................................................................440
13
FUNCTIONAL TIMING...................................................................................................................441
13.1 SERIAL LINE INTERFACE.................................................................................................................441
13.2 ATM UTOPIA LEVEL 3 SYSTEM INTERFACE .....................................................................................441
13.3 PACKET OVER SONET/SDH (POS) LEVEL 3 SYSTEM INTERFACE..................................................443
13.4 SECTION AND LINE DATA COMMUNICATION CHANNELS.....................................................................446
13.5 S/UNI-2488 CONCEPTUAL REGIONS .............................................................................................446
14
TEST FEATURES DESCRIPTION.................................................................................................447
FUNCTIONAL TIMING...................................................................................................................448
ABSOLUTE MAXIMUM RATINGS ................................................................................................449
D.C. CHARACTERISTICS.............................................................................................................450
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Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
ii
PMC [ PMC-SIERRA, INC ]
