PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
•
•
Counts number of received cells, idle cells, erred cells and dropped cells.
Provides UTOPIA Level 3 and POS-PHY Level 3 32-bit wide datapath interfaces (clocked up to 104
MHz) with parity support to read extracted cells from an internal 8 cell FIFO buffer.
1.5
The Receive POS Processor
•
•
Supports packet based link layer protocols using byte synchronous HDLC framing.
Performs self-synchronous POS data de-scrambling on the received STS-48c/STM16c-16c payloads
using the x43+1 polynomial.
•
•
•
•
•
Performs flag sequence detection and terminates the received POS frames.
Performs frame check sequence (FCS) validation for CRC-CCITT and CRC-32 polynomials.
Performs control escape de-stuffing or byte de-stuffing of the POS stream.
Detects packet abort sequence.
Checks for minimum and maximum packet lengths. Optionally deletes short packets and marks
those exceeding the maximum length as erred.
•
•
Permits FCS stripping on the POS-PHY output data stream.
Provides a SATURN POS-PHY Level 3 compliant 32-bit datapath interface (clocked up to 104 MHz)
with parity support to read packet data from an internal 256 byte FIFO buffer.
1.6
The Transmit ATM Processor
•
•
•
•
Provides idle/unassigned cell insertion.
Optionally provides HCS generation/insertion, and ATM cell payload scrambling.
Counts the number of transmitted cells.
Provides UTOPIA Level 3 and POS-PHY Level 3 32-bit wide datapath interfaces (clocked up to 104
MHz) with parity support for writing cells into an internal channel FIFO.
1.7
The Transmit POS Processor
•
Supports any packet based link layer protocol using byte synchronous and bit synchronous framing
like PPP, HDLC and Frame Relay.
•
Performs self-synchronous POS data scrambling using the 1+X43 polynomial.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
4
PMC [ PMC-SIERRA, INC ]
