PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
LIST OF FIGURES
FIGURE 1: STS-48 (STM-16-16C) ATM (UTOPIA LEVEL 3) SWITCH PORT APPLICATION
FIGURE 2: STS-48 (STM-16-16C) PACKET OVER SONET (POS-PHY LEVEL 3) ROUTER
APPLICATION
11
12
13
FIGURE 3:NORMAL OPERATION
FIGURE 4:LOOPBACK MODES
14
FIGURE 5: APS WORKING
15
FIGURE 6: APS PROTECT
16
FIGURE 7: TYPICAL STS-48C (STM-16C) JITTER TOLERANCE
FIGURE 8: STS-48C (STM-16-16C) ON RTOH
50
53
FIGURE 9: POINTER INTERPRETATION STATE DIAGRAM
FIGURE 10: CONCATENATION POINTER INTERPRETATION STATE DIAGRAM
FIGURE 11: POINTER GENERATION STATE DIAGRAM
FIGURE 12: CELL DELINEATION STATE DIAGRAM
FIGURE 13: PPP/HDLC OVER SONET FRAME FORMAT
FIGURE 14: CRC DECODER
55
58
64
66
68
69
FIGURE 15: STS-48C (STM-16-16C) ON TTOH
73
FIGURE 16: CRC GENERATOR
78
FIGURE 17: GENERIC LVDS LINK BLOCK DIAGRAM
FIGURE 18 ATM MAPPING
FIGURE 19 PACKET OVER SONET MAPPING
430
433
434
438
438
441
442
444
445
454
455
458
460
462
FIGURE 20: A 52 BYTE ATM DATA STRUCTURE
FIGURE 21: A 63 BYTE PACKET DATA STRUCTURE
FIGURE 22 SINGLE-PHY UTOPIA LEVEL 3 RECEIVE FUNCTIONAL TIMING
FIGURE 23 SINGLE-PHY UTOPIA LEVEL 3 TRANSMIT FUNCTIONAL TIMING
FIGURE 24 SINGLE PHY POS-PHY LEVEL 3 RECEIVE FUNCTIONAL TIMING
FIGURE 25 SINGLE PHY POS-PHY LEVEL 3 TRANSMIT FUNCTIONAL TIMING
FIGURE 26: INTEL MICROPROCESSOR INTERFACE READ TIMING
FIGURE 27: INTEL MICROPROCESSOR INTERFACE WRITE TIMING
FIGURE 28: RECEIVE SYSTEM INTERFACE TIMING DIAGRAM
FIGURE 29: TRANSMIT SYSTEM INTERFACE TIMING
FIGURE 30: JTAG PORT INTERFACE TIMING
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
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PMC [ PMC-SIERRA, INC ]
