PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
Indirect Register 04H: RHPP Expected PSL and PDI
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Unused
Unused
PDIRANGE
PDI[4]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDI[3]
PDI[2]
PDI[1]
Bit 8
PDI[0]
Bit 7
EPSL[7]
EPSL[6]
EPSL[5]
EPSL[4]
EPSL[3]
EPSL[2]
EPSL[1]
EPSL[0]
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register is only used by the STS-1/STM-0 #1 slice. For all other slides, this register is
invalid.
EPSL[7:0]:
The expected path signal label (EPSL[7:0]) bits represent the expected path signal label. The
expected PSL and the expected PDI validate the received or the accepted PSL to declare
PLM-P, UNEQ-P and PDI-P defects according Table 1.
PDI[4:0], PDIRANGE:
The payload defect indication (PDI[4:0]) bits and the payload defect indication range
(PDIRANGE) bit determine the expected payload defect indication according to Table 2.
When PDIRANGE is set to logic 1, the PDI range is enabled and the expected PDI range is
from E1H to E0H+PDI[4:0]. When PDIRANGE is set to logic 0, the PDI range is disable and
the expected PDI value is E0H+PDI[4:0]. The expected PSL and the expected PDI validate
the received or the accepted PSL to declare PLM-P, UNEQ-P and PDI-P defects according
Table 1.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
224
PMC [ PMC-SIERRA, INC ]
