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PM5381 参数 Datasheet PDF下载

PM5381图片预览
型号: PM5381
PDF下载: 下载PDF文件 查看货源
内容描述: SATURN用户网络接口,用于2488 Mbit / s的 [SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S]
分类和应用: 网络接口
文件页数/大小: 487 页 / 2424 K
品牌: PMC [ PMC-SIERRA, INC ]
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PMC-Sierra, Inc.  
PRELIMINARY  
PM5381 S/UNI-2488  
DATASHEET  
PMC-2000489  
ISSUE 1  
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S  
LRDII:  
The line remote defect indication interrupt status (LRDII) bit is an event indicator. LRDII is set  
to logic 1 to indicate any change in the status of LRDIV. The interrupt status bit is  
independent of the interrupt enable bit. LRDII is cleared to logic 0 when this register is read.  
APSBFI:  
The APS byte failure interrupt status (APSBFI) bit is an event indicator. APSBFI is set to logic  
1 to indicate any change in the status of APSBFV. The interrupt status bit is independent of  
the interrupt enable bit. APSBFI is cleared to logic 0 when this register is read.  
COAPSI:  
The change of APS bytes interrupt status (COAPSI) bit is an event indicator. COAPSI is set  
to logic 1 to indicate a new APS bytes. The interrupt status bit is independent of the interrupt  
enable bit. COAPSI is cleared to logic 0 when this register is read.  
COSSMI:  
The change of SSM message interrupt status (COSSMI) bit is an event indicator. COSSMI is  
set to logic 1 to indicate a new SSM message. The interrupt status bit is independent of the  
interrupt enable bit. COSSMI is cleared to logic 0 when this register is read.  
SBIPEI:  
The section BIP error interrupt status (SBIPEI) bit is an event indicator. SBIPEI is set to logic  
1 to indicate a section BIP error. The interrupt status bit is independent of the interrupt  
enable bit. SBIPEI is cleared to logic 0 when this register is read.  
LBIPEI:  
The line BIP error interrupt status (LBIPEI) bit is an event indicator. LBIPEI is set to logic 1 to  
indicate a line BIP error. The interrupt status bit is independent of the interrupt enable bit.  
LBIPEI is cleared to logic 0 when this register is read.  
LREIEI:  
The line REI error interrupt status (LREIEI) bit is an event indicator. LREIEI is set to logic 1 to  
indicate a line REI error. The interrupt status bit is independent of the interrupt enable bit.  
LREIEI is cleared to logic 0 when this register is read.  
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use  
142  
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