S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
7 Description
The PM5380 S/UNI-8x155 SATURN User Network Interface is a monolithic integrated circuit
that implements SONET/SDH processing, ATM mapping and Packet over SONET/SDH
mapping functions at the STS-3c/STM-1 155.52 Mbit/s rate for eight channels.
The S/UNI-8x155 receives SONET/SDH streams using a bit serial interface, recovers the clock
and data and processes section, line, and path overhead. The S/UNI-8x155 performs framing
(A1, A2), de-scrambling, detects alarm conditions, and monitors section, line, and path bit
interleaved parity (B1, B2, B3), accumulating error counts at each level for performance
monitoring purposes. Line and path remote error indications (M1, G1) are also accumulated.
The S/UNI-8x155 interprets the received payload pointers (H1, H2) and extracts the
synchronous payload envelope which carries the received ATM cell or POS frame payload.
When used to implement an ATM UNI or NNI, the S/UNI-8x155 frames to the ATM payload
using cell delineation. The ATM cell payloads are descrambled and are written to a 64 cell (4
cells per channel) FIFO buffer. The received cells are read from the FIFO using a 32-bit wide
UTOPIA Level 3 (clocked up to 104 MHz) or 32-bit wide POS-PHY Level 3 (clocked up to 104
MHz) system side interface. Counts of received ATM cell headers that are erred are
accumulated for performance monitoring purposes.
When used to implement packet transmission over a SONET/SDH link, the S/UNI-8x155
extracts Packet over SONET/SDH (POS) frames from the SONET/SDH synchronous payload
envelope. Frames are verified for correct construction and size. The control escape characters
are removed. The frame check sequence is optionally verified for correctness and the extracted
packets are placed in a 2 Kbyte (256 bytes per channel) receive FIFO. The received packets are
read from the FIFO through a 32-bit POS-PHY Level 3 (clocked up to 104 MHz) system side
interface. Valid and FCS errored packet counts are provided for performance monitoring. The
S/UNI-8x155 Packet over SONET/SDH implementation is flexible enough to support several
link layer protocols, including HDLC, PPP and Frame Relay.
The S/UNI-8x155 synthesizes the transmit clock from a 77.76MHz frequency reference and
performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates
section, line, and path bit interleaved parity codes (B1, B2, B3) as required to allow
performance monitoring at the far end. Line and path remote error indications (M1, G1) are
also inserted. The S/UNI-8x155 generates the payload pointer (H1, H2) and inserts the
synchronous payload envelope that carries the ATM cell or POS frame payload. The S/UNI-
8x155 also supports the insertion of a large variety of errors into the transmit stream, such as
framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for
system diagnostics and tester applications.
When used to implement an ATM UNI or NNI, ATM cells are written to an internal 64 cell
FIFO (4 cells per channel) using a 32-bit wide UTOPIA Level 3 (clocked up to 104 MHz) or
32-bit width POS-PHY Level 3 (clocked up to 104 MHz) system side interface. Idle/unassigned
cells are automatically inserted when the internal FIFO contains less than one complete cell.
The S/UNI-8x155 provides generation of the header check sequence and scrambles the payload
of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or
bypassed.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
37
PMC [ PMC-SIERRA, INC ]
