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PM5371-RI 参数 Datasheet PDF下载

PM5371-RI图片预览
型号: PM5371-RI
PDF下载: 下载PDF文件 查看货源
内容描述: SONET / SDH支路单元交叉连接 [SONET/SDH TRIBUTARY UNIT CROSS CONNECT]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路开关异步传输模式
文件页数/大小: 93 页 / 304 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM5371TUDX  
DATA SHEET  
PMC-920525  
ISSUE 6  
SONET/SDH TRIBUTARY UNIT CROSS CONNECT  
Pin Name Type  
Pin Function  
No.  
SINL[0]  
Input  
121 The left systolic input bus (SINL[8:0]) carries  
SONET/SDH frame data in byte serial format. The  
SINL[8] bit is a parity bit which is not passed through  
SINL[1]  
SINL[2]  
SINL[3]  
SINL[4]  
SINL[5]  
SINL[6]  
SINL[7]  
SINL[8]  
SINR[0]  
SINR[1]  
SINR[2]  
SINR[3]  
SINR[4]  
SINR[5]  
SINR[6]  
SINR[7]  
SINR[8]  
122  
123  
124  
125  
156  
157  
158  
159  
80  
the TUDX. The TUDX may be configured to check for  
even or odd input bus parity and generate interrupts  
when parity errors occur. The SINL[8:0] bus is  
sampled on the rising edge of SCLK. Data on the  
SINL[8:0] bus is re-timed and may be routed to the  
DOUTL[8:0] in place of information switched from the  
DINT[8:0] bus, and is provided for constructing larger  
switching arrays using systolic data flow.  
Input  
The right systolic input bus (SINR[8:0]) carries  
SONET/SDH frame data in byte serial format. The  
SINR[8] bit is a parity bit which is not passed through  
the TUDX. The TUDX may be configured to check for  
even or odd input bus parity and generate interrupts  
when parity errors occur. The SINR[8:0] bus is  
sampled on the rising edge of SCLK. Data on the  
SINR[8:0] bus is re-timed and may be routed to the  
DOUTR[8:0] in place of information switched from the  
DINB[8:0] bus, and is provided for constructing larger  
switching arrays using systolic data flow.  
79  
78  
77  
76  
46  
45  
44  
43  
SOUTT[0] Output 117 The left systolic output bus (SOUTT[8:0]) carries  
SONET/SDH frame data in byte serial format. The  
SOUTT[1]  
SOUTT[2]  
SOUTT[3]  
SOUTT[4]  
SOUTT[5]  
SOUTT[6]  
SOUTT[7]  
SOUTT[8]  
116  
115  
114  
113  
112  
111  
110  
109  
SOUTT[8] bit is a parity bit which is generated by the  
TUDX. The TUDX may be configured to generate  
even or odd parity. The SOUTT[8:0] bus is updated on  
the rising edge of SCLK. The SOUTT[8:0] bus carries  
a re-timed copy of the information sampled on the  
DINT[8:0] bus and is provided for constructing larger  
switching arrays using systolic data flow. The SOUTT  
bus can be disabled to save power when not used.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
15  
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