PM5371TUDX
DATA SHEET
PMC-920525
ISSUE 6
SONET/SDH TRIBUTARY UNIT CROSS CONNECT
8
PIN DESCRIPTION
Pin Name Type
Pin Function
No.
SCLK
Input
97
The system clock (SCLK) provides timing for TUDX
internal operation. SCLK is a 19.44 MHz, nominally
50% duty cycle clock.
VCLK
SFP
The test vector clock (VCLK) provides timing for TUDX
production test.
Input
42
The system frame pulse (SFP) determines the frame
boundaries on the DINT[8:0] and DINB[8:0] buses
(and SINL[8:0] and SINR[8:0] buses) when OFSEB is
high. SFP determines the frame boundaries on the
SOUTT[8:0] and SOUTB[8:0] buses when OFSEB is
low. SFP must be brought high once every frame (125
µs) to mark the first C1 byte of the transport envelope
frame of the buses in question. In systolic
applications where OFSEB is high, SFP marks the C1
byte of the SINL[8:0] and SINR[8:0] buses (or the
DINT[8:0] and DINB[8:0] buses) after the
programmable systolic delay has been inserted. See
the Application Examples and Functional Timing
sections for more information. SFP is sampled on the
rising edge of SCLK.
OFSEB
Input
160 The active low output frame synchronization enable
(OFSEB) signal selects the system frame alignment
marked by SFP. When OFSEB is high, SFP is
coincident with the input frame pulse (IFP). When
OFSEB is low, SFP is coincident with the output frame
pulse (OFP). In most applications, OFSEB should be
held high. The OFSEB input has an integral pull up
resistor.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
11
PMC [ PMC-SIERRA, INC ]
