PM5371TUDX
DATA SHEET
PMC-920525
ISSUE 6
SONET/SDH TRIBUTARY UNIT CROSS CONNECT
Systolic Delay Control Register of the upper right hand TUDX is programmed to
insert a 5 clock period delay in the SINL/SINR buses, and the SOUTT/SOUTB
buses.
Figure 2
- 2 X 2TUDX Switch Array Using Bused Interconnect
'5'
'5'
'0'
'0'
SINL
SINR
SINL
SINR
SCLK
SFP
SCLK
SFP
OFP
IFP
OFP
IFP
TUDX
TUDX
DINT
SOUTT
SOUTB
ODEB
AOBEB
DINT
SOUTT
SOUTB
ODEB
AOBEB
DINB
DINB
OFSEB
OFSEB
SOBEB
SOBEB
DOUTL
DOUTL
DOUTR
DOUTR
'0'
'0'
SINL
SINR
SINL
SINR
SCLK
SFP
SCLK
SFP
OFP
IFP
OFP
IFP
TUDX
TUDX
DINT
DINB
SOUTT
SOUTB
ODEB
DINT
DINB
SOUTT
SOUTB
ODEB
OFSEB
SOBEB
OFSEB
SOBEB
AOBEB
AOBEB
DOUTL
DOUTL
DOUTR
DOUTR
'5'
'5'
Bused interconnect of TUDX devices is illustrated above. In this 2 x 2 array of
devices, PCM data is distributed left to right on a common bus and gathered top
to bottom using a wired-OR type bus. Using this interconnect approach,
additional devices must be used to drive the distribution bus and sample the
wired-OR bus. To maximize the size of array that can be achieved using a wired-
OR bus, the AOUTL and AOUTR buses may be parallel connected with the
DOUTL and DOUTR buses on a bit by bit basis in order to provide higher drive
levels. Due to the higher fan out of these buses, and the RC delay on the wired-
OR bus, this approach cannot be extended to very large arrays without additional
circuitry. This bused array approach provides the minimum data delay through
the array (when a cross connection is made between the DINT/DINB buses and
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
5
PMC [ PMC-SIERRA, INC ]
