PM5371TUDX
DATA SHEET
PMC-920525
ISSUE 6
SONET/SDH TRIBUTARY UNIT CROSS CONNECT
4
APPLICATION EXAMPLES
Larger switching arrays can be constructed in a variety of manners using arrays
of TUDX devices. Systolic or bused interconnect methods can be used, or a
hybrid of the two approaches.
Figure 1
- 2 X 2TUDX Switch Array Using Systolic Interconnect
'0'
'0'
SINL
SINR
SINL
SINR
SCLK
SFP
IFP
OFP
SCLK
SFP
IFP
OFP
TUDX
TUDX
DINT
SOUTT
SOUTB
ODEB
AOBEB
DINT
SOUTT
SOUTB
ODEB
AOBEB
'15'
'0'
'5'
DINB
DINB
OFSEB
OFSEB
SOBEB
SOBEB
DOUTL
DOUTL
DOUTR
DOUTR
'5'
'10'
SINL
SINR
SINL
SINR
SCLK
SFP
IFP
OFP
SCLK
SFP
IFP
OFP
TUDX
TUDX
DINT
SOUTT
SOUTB
ODEB
DINT
SOUTT
SOUTB
ODEB
AOBEB
'15'
'0'
'10'
DINB
DINB
OFSEB
OFSEB
SOBEB
AOBEB
SOBEB
DOUTL
DOUTL
DOUTR
DOUTR
'15'
'15'
Systolic interconnect of TUDX devices is illustrated above. In this 2 x 2 array of
devices, PCM data is distributed left to right and gathered top to bottom with the
PCM data being re-timed as it passes through each device. Each PCM data bus
drives a single device, regardless of the size of the array and thus systolic
interconnect allows large arrays to be implemented without the use of additional
devices. In this example no systolic delay is required for the upper left hand and
lower right hand TUDX in the array. The Systolic Delay Control Register of the
lower left hand TUDX is programmed to insert a 5 clock period delay in the
DINT/DINB buses, and a 5 clock period delay in the DOUTL/DOUTR buses. The
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
4
PMC [ PMC-SIERRA, INC ]
