STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
ALE
Input D17
Address Latch Enable (ALE). This signal is active
high and latches the address bus A[13:0] when low.
When ALE is high, the internal address latches are
transparent. It allows the TEMAP to interface to a
multiplexed address/data bus. The ALE input has an
integral pull up resistor.
JTAG Interface
TCK
Input C3
Input C2
Test Clock (TCK). This signal provides timing for test
operations that can be carried out using the IEEE
P1149.1 test access port.
Test Mode Select (TMS). This signal controls the test
operations that can be carried out using the IEEE
P1149.1 test access port. TMS is sampled on the rising
edge of TCK. TMS has an integral pull up resistor.
Test Data Input (TDI). This signal carries test data into
the TEMAP via the IEEE P1149.1 test access port. TDI
is sampled on the rising edge of TCK. TDI has an
integral pull up resistor.
Test Data Output (TDO). This signal carries test data
out of the TEMAP via the IEEE P1149.1 test access
port. TDO is updated on the falling edge of TCK. TDO
is a tri-state output which is inactive except when
scanning of data is in progress.
TMS
TDI
Input C4
Output B3
TDO
TRSTB
Input B1
Active low Test Reset (TRSTB). This signal provides
an asynchronous TEMAP test access port reset via the
IEEE P1149.1 test access port. TRSTB is a Schmitt
triggered input with an integral pull up resistor. TRSTB
must be asserted during the power up sequence.
Note that if not used, TRSTB must be connected to the
RSTB input.
Miscellaneous Pins
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
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PMC [ PMC-SIERRA, INC ]
