PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 1FAH, 2FAH, 3FAH: RTOP, TU #4 in TUG2 #1 to TUG2 #7, PSLU
Interrupt
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
PSLU7I
PSLU6I
PSLU5I
PSLU4I
PSLU3I
PSLU2I
PSLU1I
X
0
0
0
0
0
0
0
R
R
R
R
R
R
R
This register is used to identify and acknowledge path signal label unstable
interrupts for the tributaries TU #4 in TUG2 #1 TO TUG2 #7.
PSLU1I-PSLU7I:
The PSLU1I to PSLU7I bits identify the source of path signal label mismatch
interrupts. In TU3 mode, these bits are unused and will return a logic 0 when
read. When the corresponding TUG2 tributary group is configured for TU2
(VT6), VT3 or TU12 (VT2) mode, the associated PSLUxI bit is unused and will
return a logic 0 when read. When operational, the PSLU1I to PSLU7I bits
report and acknowledge PSLU interrupt of TU #4 in TUG2 #1 to TUG2 #7,
respectively. Interrupts are generated when the received PSL becomes
unstable or returns to stable. An PSLUxI bit is set high when a change of PSL
unstable state on the associated tributary (TU #4 in TUG2 #x) occurs and are
cleared immediately following a read of this register, which also
acknowledges and clears the interrupt. PSLUxI remains valid when interrupts
are not enabled (PSLUE set low) and may be polled to detect path signal
label stable/unstable events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
292
PMC [ PMC-SIERRA, INC ]
