PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 1C2H, 1CAH, 1D2H, 1DAH, 1E2H, 1EAH, 1F2H:
Register 2C2H, 2CAH, 2D2H, 2DAH, 2E2H, 2EAH, 2F2H:
Register 3C2H, 3CAH, 3D2H, 3DAH, 3E2H, 3EAH, 3F2H:
RTOP, TU #4 in TUG2 #1 to TUG2 #7, Expected Path Signal Label
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
EPSL[2]
EPSL[1]
EPSL[0]
X
X
X
X
X
0
R/W
R/W
R/W
0
0
This set of registers configures the expected path signal label of TU #4 in TUG2
#1 to TUG2 #7. These registers have no effect in TU3 mode. When the
corresponding TUG2 tributary group is configured to TU2 (VT6), VT3 or TU12
(VT2) mode, the associated register in this set has no effect.
EPSL[2:0]:
The EPSL[2:0] bits specifies the expected path signal label of tributary TU #4
in the corresponding TUG2. The expected PSL is compared with the accepted
PSL to determine the PSLM state.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
284
PMC [ PMC-SIERRA, INC ]
