PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 1C1H, 1C9H, 1D1H, 1D9H, 1E1H, 1E9H, 1F1H:
Register 2C1H, 2C9H, 2D1H, 2D9H, 2E1H, 2E9H, 2F1H:
Register 3C1H, 3C9H, 3D1H, 3D9H, 3E1H, 3E9H, 3F1H:
RTOP, TU #4 in TUG2 #1 to TUG2 #7, Configuration and Alarm Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R
R
R
RDIZ7EN
TUPTE
PDIVEN
PSLUV
PSLMV
0
0
0
X
X
X
X
X
ERDIV[2]
ERDIV[1]/RFIV
ERDIV[0]/RDIV
R
R
This set of registers configures and reports the alarm status of TU #4 in TUG2 #1
to TUG2 #7. These registers have no effect in TU3 mode. When the
corresponding TUG2 tributary group is configured to TU2 (VT6), VT3 or TU12
(VT2) mode, the associated register in this set has no effect.
RDIV:
The RDIV bit indicates the remote defect indication status of tributary TU #4 in
the corresponding TUG2 when RDIZ7EN is low. RDIV is set high when the
RDI bit in the V5 byte is set high for five or ten consecutive multiframes as
determined by the RDI10 bit in the RTOP and RTTB Configuration registers
(addresses 0CH, 0DH, and 0EH). RDIV is set low when the RDI bit is set low
for five or ten consecutive multiframes as determined by the RDI10 bit
RFIV:
The RFIV bit indicates the remote failure indication status of tributary TU #4 in
the corresponding TUG2 when RDIZ7EN is set low. RFIV is set high when the
RFI bit in the V5 byte is set high for five or ten consecutive multiframes as
determined by the RDI10 bit in the RTOP and RTTB Configuration registers
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
281
PMC [ PMC-SIERRA, INC ]
