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PM5363-BI 参数 Datasheet PDF下载

PM5363-BI图片预览
型号: PM5363-BI
PDF下载: 下载PDF文件 查看货源
内容描述: SONET / SDH支路单元荷载处理器, 622兆比特/ s接口 [SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 459 页 / 3435 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM5363 TUPP+622  
TUPP+622  
DATASHEET  
PMC-1981421  
ISSUE 4  
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S  
INTERFACES  
Register 1BAH, 2BAH, 3BAH: RTOP, TU #3 in TUG2 #1 to TUG2 #7, PSLU  
Interrupt  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Unused  
PSLU7I  
PSLU6I  
PSLU5I  
PSLU4I  
PSLU3I  
PSLU2I  
PSLU1I  
X
0
0
0
0
0
0
0
R
R
R
R
R
R
R
This register is used to identify and acknowledge path signal label unstable  
interrupts for the tributaries TU #3 in TUG2 #1 TO TUG2 #7.  
PSLU1I-PSLU7I:  
The PSLU1I to PSLU7I bits identify the source of path signal label mismatch  
interrupts. In TU3 mode, these bits are unused and will return a logic 0 when  
read. When the corresponding TUG2 tributary group is configured for TU2  
(VT6) or VT3 mode, the associated PSLUxI bit is unused and will return a  
logic 0 when read. When operational, the PSLU1I to PSLU7I bits report and  
acknowledge PSLU interrupt of TU #3 in TUG2 #1 to TUG2 #7, respectively.  
Interrupts are generated when the received PSL becomes unstable or returns  
to stable. An PSLUxI bit is set high when a change of PSL unstable state on  
the associated tributary (TU #3 in TUG2 #x) occurs and are cleared  
immediately following a read of this register, which also acknowledges and  
clears the interrupt. PSLUxI remains valid when interrupts are not enabled  
(PSLUE set low) and may be polled to detect path signal label stable/unstable  
events.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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