PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
These registers report the number of block interleave parity (BIP-2) errors
detected in TU #3 in TUG2 #1 to TUG2 #7 in the previous accumulation interval.
These registers contain invalid data in TU3 mode. When the corresponding
TUG2 tributary group is configured to TU2 (VT6) or VT3 mode, the data in the
associated registers are invalid. These registers do not saturate.
BIP[10:0]:
The BIP[10:0] bits report the number of tributary path bit-interleaved parity
errors that have been detected since the last time the BIP-2 registers were
polled. The BIP-2 registers are polled by writing to the Input Signal Activity
Monitor, Accumulate Trigger register. The write access transfers the internally
accumulated error count to the BIP-2 registers within 10 µs and resets the
internal counter simultaneously to begin a new cycle of error accumulation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
269
PMC [ PMC-SIERRA, INC ]
