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PM5363-BI 参数 Datasheet PDF下载

PM5363-BI图片预览
型号: PM5363-BI
PDF下载: 下载PDF文件 查看货源
内容描述: SONET / SDH支路单元荷载处理器, 622兆比特/ s接口 [SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 459 页 / 3435 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM5363 TUPP+622  
TUPP+622  
DATASHEET  
PMC-1981421  
ISSUE 4  
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S  
INTERFACES  
These registers report the number of block interleave parity (BIP-2) errors  
detected in TU #3 in TUG2 #1 to TUG2 #7 in the previous accumulation interval.  
These registers contain invalid data in TU3 mode. When the corresponding  
TUG2 tributary group is configured to TU2 (VT6) or VT3 mode, the data in the  
associated registers are invalid. These registers do not saturate.  
BIP[10:0]:  
The BIP[10:0] bits report the number of tributary path bit-interleaved parity  
errors that have been detected since the last time the BIP-2 registers were  
polled. The BIP-2 registers are polled by writing to the Input Signal Activity  
Monitor, Accumulate Trigger register. The write access transfers the internally  
accumulated error count to the BIP-2 registers within 10 µs and resets the  
internal counter simultaneously to begin a new cycle of error accumulation.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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